Conventionally, image display devices wherein a liquid crystal element, an EL (electro luminescent) element, and an LED (light emitting diode) element, etc., are arranged in a matrix form has been used. Such a matrix-type image display device will be explained below through an example of a liquid crystal display device.
FIG. 11 is a front view showing a schematic structure of a generally used liquid crystal display device 1. As shown in FIG. 11, the liquid crystal display device 1 is mainly composed of a pixel array ARY, a scanning signal line driving circuit gd, a data signal line driving circuit sd and a control circuit 2.
On the pixel array ARY, a plurality of pixels PIX are formed. The scanning signal line driving circuit sd and the data signal line driving circuit sd are provided for display driving the pixels PIX. The control circuit 2 is provided for controlling the driving of these signal line driving circuits gd and sd.
On the pixel array ARY, a plurality of scanning signal lines GL.sub.j (j=1, 2, . . . , n) and a plurality of data signal lines SL.sub.i (i=1, 2, . . . , m) are formed so as to cross at a right angle. Then, in a region surrounded by the adjoining two scanning signal lines GL.sub.j and GL.sub.j+1 and two data signal lines SL.sub.j and SL.sub.j+1, the pixel PIX is formed. As described, the pixels PIX are formed in a matrix form on the pixel array ARY.
The data signal line driving circuit sd samples and if necessary amplifies the image signal DAT as input, and outputs it to each data signal line SL.sub.i. This sampling is carried out in sync with the timing signal such as a clock signal CKS, etc., from the control circuit 2. The scanning signal line driving circuit gd sequentially selects the scanning signal lines GL.sub.j and controls the opening/closing of the switching element (to be described later) provided in the pixel PIX. This control is performed in sync with the timing signal such as a clock signal CKG, GPS, etc., from the control circuit 2.
By the described operations of the circuits sd and gd, the image signal (data) DAT is output to the data signal line SL.sub.i to be written in each pixel PIX. Then, until the next scanning timing, the image data DAT is held in each pixel PIX to carry out a display output.
As a system of outputting an image data DAT to each data signal line SL.sub.i by the data signal line driving circuit sd, a dot sequential driving system and a line sequential driving system have been known. In the dot sequential driving system, the image data DAT are sequentially output to a pixel of a line selected by the scanning signal line GL.sub.j. In the line sequential driving system, image data DAT are output to pixels on the line as selected at once. An example of the data signal line driving circuit of the dot sequential driving system of a simple circuit structure will be explained with reference to FIG. 12.
FIG. 12 is a block diagram showing an electric structure of a data signal line driving circuit sd of the dot sequential driving system as a typical conventional example. As shown in the figure, an analog switch asw.sub.i is formed along each data signal line SL.sub.i. When the analog switch asw.sub.i conducts, the image data DAT is sampled to be output to each data signal line SL.sub.i. In order to control these analog switches asw.sub.i, scanning circuits srs.sub.i (i=1, 2, . . . , m) and buffers bufs.sub.i respectively corresponding to analog switches asw.sub.i are formed.
The scanning circuits srs.sub.i are mutually cascade-connected. To each scanning circuit srs.sub.i, a common clock signal CKS is input. To the leading end of the scanning circuit srs.sub.1, a start pulse SPS prepared based on a horizontal scanning signal is applied.
When the start pulse SPS is applied to the scanning circuit srs.sub.1, a sampling pulse is output from each scanning circuit srs.sub.i. The output of the sampling pulse in each scanning circuit srs.sub.i is sequentially carried out from the scanning circuit srs.sub.1 of the starting end. The sampling pulse is held and amplified in the buffer bufs.sub.i, and inverses when necessary to be applied to each analog switch asw.sub.i.
The scanning signal line driving circuit gd shown in FIG. 11, for example, has a structure of FIG. 13. As shown in the figure, the scanning signal line driving circuit gd includes scanning circuits srg.sub.k (K=1, 2, . . . , n+1) having the same arrangement as the aforementioned scanning circuit srs.sub.i, and two kinds of AND circuits and1.sub.j and and2.sub.j, and a buffer bufg.sub.j respectively corresponding to the scanning signal lines GL.sub.i.
Each scanning circuit srg.sub.k is cascade-connected to the scanning circuit srs.sub.i. Upon inputting the start pulse SPG prepared based on a vertical sync signal to the leading end scanning circuit srg.sub.1, the start pulse SPG responds to the clock signal CKG prepared based on the horizontal scanning signal. The start pulses SPG are sequentially output to the scanning circuits srg.sub.2, srg.sub.3, . . . in the post stage.
The respective outputs from the adjoining scanning circuits srg.sub.j and srg.sub.j+1 are computed in an AND circuit and1.sub.j. Thereafter, the output from the AND circuit and1.sub.j is computed with the clock signal GPS in the AND circuit and2.sub.j to be input respectively to the buffer bufg.sub.j.
In response to the clock signal CKG, each scanning circuit srg.sub.k outputs the start pulse SPG with a lag of a half period from the srg.sub.k-1 in the post stage. Namely, the pulse to be output from the scanning circuit srg.sub.j rises at a timing of a rise of the clock signal CKG and is held for one period until the next rise timing. In contrast, the scanning circuit srg.sub.j+1 in the next stage outputs a pulse for one period from a timing of a fall of the clock signal CKG. Namely, the pulse having a time difference of a half period between the adjoining scanning circuits srg.sub.j and srg.sub.j+1 is input to the AND circuit and1.sub.j. Therefore, from the AND circuit and1.sub.j, the pulse of a length of a 1/2 period of the clock signal CKG is output to the AND circuit and2.sub.j.
The speed of the clock signal GPS is, for example, twice as high as that of the clock signal CKG. Therefore, the pulse to be output from the AND circuit and2.sub.j is shorter than a 1/2 period of the clock signal CKG, thereby preventing a generation of a period in which pulses are overlapped between the adjoining AND circuits and2.sub.j and and2.sub.j+1. The output from the AND circuit and2.sub.j is amplified in the buffer bufg.sub.j and inverses if necessary to be output to each scanning signal line GL.sub.j.
Here, respective driving voltages for the signal line driving circuits gd and sd will be considered. The driving voltage for the data signal line driving circuit sd is selected to satisfy the conditions of: (a) the scanning circuit srs.sub.i can be driven at a frequency as desired, and (b) the image data DAT of both positive and negative polarities can be output to the data signal line SL.sub.i. Specifically, the desirable frequency is around 25.2 MHz in the case of the VGA (Video Graphical Array) display in the case where the scanning signal line driving circuits gd are not aligned in parallel or the sampling is not carried out simultaneously. In general, the driving voltage is determined based on a request from the analog switch asw.sub.i rather than a request from the scanning circuit srs.sub.i.
For example, when the liquid crystal driving voltage is .+-.5V, and the voltage of the counter electrode is 0 V, the level of the image signal at the data signal line SL.sub.i is in a range of from -5 to +5V, and the driving voltage of the data signal line driving circuit sd is in a range of from -5 to +5 V.
In contrast, in the scanning signal line driving circuit gd, the driving voltage on the positive polarity side is determined such that the switching element in the pixel PIX writes the image data of positive polarity to the pixel capacitor. Additionally, the driving voltage of the negative polarity side is determined such that the image data having a negative polarity can be held for 1 frame period.
For example, when a threshold voltage of the switching element is +3V, the driving signal level of the scanning signal line driving circuit gd is determined as follows. Namely, on the side of the positive polarity, the voltage becomes around 10 V obtained by adding the level +5V of the image signal and the margin +2V to +3V. On the other hand, on the negative polarity side, the voltage becomes around -8V obtained by adding the image data DAT level -5V and the margin -6V to +3V. Here, the driving signal level suggests respective output signal levels of the signal line driving circuits gd and sd, which may be equivalent to the respective driving voltages for these signal line driving circuits gd and sd.
Each of the described driving signal levels and driving voltages show merely examples, and an optimal value for each driving voltage varies depending on factors such as the driving method, the arrangement of the driving circuit, characteristics of the transistor, the kind of the liquid crystals, etc.
As described, in the liquid crystal display device, the liquid crystals are display driven as described above. In general, the driving voltage of the data signal line driving circuit sd and the driving voltage of the scanning signal line driving circuit gd are at mutually different levels, and are larger than the voltage that is generally used in an integration circuit, that is, for example, 3.3 V or 5 V.
This is because it is required to apply respective voltages of around 5V as a driving voltage of the signal line driving circuits sd and gd. Another cause is a difference in structure between the data signal line driving circuit sd and the scanning signal line driving circuit gd. Namely, the analog switch asw.sub.i of the data signal line driving circuit sd has a CMOS structure for handling the image data DAT of both positive and negative polarities, while the switching element in the pixel PIX controlled by the scanning signal line driving circuit sd has a single channel structure such as NMOS, etc.
In order to obtain the described driving signal, it is required to set the respective amplitudes of the clock signals CKS, CKG, GPS, etc., and the start pulses SPS, SPG, etc., to be input to these signal line driving circuits sd and gd large and to have a level as desired. In order to obtain these clock signals CKS, CKG, GPS and the start pulses SPS, SPG, etc., it is required to increase the cost and the power consumption. This is because the control circuit 2, the interface circuit, etc., are required. The control circuit 2 is provided for controlling these signal line driving circuits sd and gd. The interface circuit is provided for shifting the output from the external circuit such as the image signal processing circuit, etc., to the voltage level as desired.
Another solution to the described conventional technique is disclosed in, for example, Japanese Unexamined Patent Publication No. 95073/1994 (Tokukaihei 6-95073). In this technique, the respective input amplitudes of the data signal line driving circuit and the scanning signal line driving circuit are adjusted to 5 V (0 V-5 V). Further, by the level shift circuit formed inside the driving circuit, it is boosted to 15 V (0V-15V), i.e., the output amplitude level as desired. By controlling the input signal in the described manner, the amplitude of the input signal is made small, and the load of the external interface circuit can be made small.
However, in the conventional techniques, the voltage level of one input signal (only the high potential side in this example) is level shifted, and the respective input signal levels of the data signal line driving circuit and the scanning signal line driving circuit are boosted to the driving signal level of the same level.
Therefore, in the described case where respective optimal values of the driving signal levels for the data signal line driving circuit and the scanning signal line driving circuit differ, the described conventional technique may not be applied.